This invention relates to MOSgated devices and more specifically relates to a novel structure for a MOSgated device with a reduced gate-to-drain capacitance.
The periodic charging/discharging of the parasitic gate-drain (Miller) capacitance of a MOSFET during each switching cycle is known to increase the power dissipated within the conventional trench-gate MOSFET structures. This decreases the efficiency of the power system and limits the operating frequency of the MOSFETs. Furthermore, the gate-drain capacitance makes the MOSFET susceptible to spurious turn-on, induced by a rapidly changing drain voltage (dv/dt induced turn-on). Sometimes, this leads to the destructive failure of the MOSFET. The novel reverse source-drain FET structures of this invention significantly reduces the gate-drain capacitance and susceptibility to spurious turn-on.
A significant portion of the gate-drain capacitance (Cgd) of a conventional MOSFET is the oxide capacitance (Cox) in the gate-drain overlap area. The oxide capacitance (Cox) is inversely proportional to the oxide thickness (tox) in the gate-drain overlap region and directly proportional to the gate-drain overlap area. In accordance with the invention, the arrangement of the source and drain electrodes (with respect to the gate electrode) is reversed. The reversed source-drain FET structure significantly lowers the gate-drain capacitance by reducing the overlap area of gate and drain and by increasing the oxide thickness between the gate and the drain electrodes.